In general, power supplies can provide stable voltage and current. In order to comply with safety, power supplies should provide open-loop protection and short-circuit protection for ensuring the power supplies and the application circuits of the load side free from influences. FIG. 1 shows a circuit diagram of the conventional power supply with open-loop protection. The conventional power supply comprises a transformer T1, a reset circuit 14, a signal generating circuit 10, an oscillator 12, a power switch Q1, a feedback detection circuit 16, a delay circuit 18, and a driving circuit 20.
As shown in FIG. 1, the transformer T1 has a primary winding NP and a secondary winding NS for storing energy and converting power. The transformer T1 is coupled to an input voltage VIN of the power supply for generating an output voltage VO. The power switch Q1 switches the transformer T1 for converting the energy stored in the primary winding NP to the secondary winding NS. The energy converted to the secondary winding NS is rectified by an output rectifier DO and an output capacitor CO for generating the output voltage VO. A current sensing resistor RS is connected to the power switch Q1 in series. The current sensing resistor RS generates a current signal VCS in response to a primary-side switching current IP of the transformer T1. In addition, the output voltage VO of the power supply provides a feedback signal VFB to the reset circuit 14 and the feedback detection circuit 16 by means of feedback.
The reset circuit 14 comprises a logic circuit 144, a power limiting comparator 146, and a pulse-width-modulation (PWM) comparator 148. The reset circuit 14 generates a clear signal CLR in response to the current signal VCS, a power limiting signal VLMT, and the feedback signal VFB for turning off a switching signal VPWM. An input terminal of the power limiting comparator 146 and an input terminal of the PWM comparator 148 are coupled to the current sensing resistor RS for receiving the current signal VCS. The other input terminal of the power limiting comparator 146 receives the power limiting signal VLMT. The other input terminal of the PWM comparator 148 receives the feedback signal VFB.
When the current signal VCS is higher than the power limiting signal VLMT, an output terminal of the power limiting comparator 146 will output an over-current signal OC with a low voltage level. Besides, when the current signal VCS is higher than the feedback signal VFB, an output terminal of the PWM comparator 148 will output a feedback control signal CNTR with a low voltage level. Both input terminals of the logic circuit 144 are coupled to the output terminals of the power limiting comparator 146 and the PWM comparator 148. Thereby, the output terminal of the logic circuit 144 will generate the clear signal CLR with a low voltage level in response to the over-current signal OC and/or the feedback control signal CNTR for turning off the switch signal VPWM. In other words, the reset circuit 14 determines the logic level of the clear signal CLR in response to the logic level of the feedback control signal CNTR or the logic level of the over-current signal OC.
The signal generating circuit 10 comprises a logic circuit 101, a flip-flop 103, and a logic circuit 105. The logic circuit 101 is an inverter. An input terminal of the logic circuit 101 is coupled to the oscillator 12 for receiving a clock signal PLS outputted by the oscillator 12. An output terminal of the logic circuit 101 is coupled to a clock input terminal CK of the flip-flop 103 for driving the flip-flop 103. An input terminal D of the flip-flop 103 is coupled to an output terminal of the delay circuit 18. An output terminal Q of the flip-flop 103 is coupled to an input terminal of the logic circuit 105. The other input terminal of the logic circuit 105 receives the clock signal PLS via the logic circuit 101. An output terminal of the logic circuit 105 generates the switching signal VPWM. The logic circuit 105 is an AND gate. The reset input terminal R of the flip-flop 103 is coupled to an output terminal of the reset circuit 14 for receiving the clear signal CLR.
The signal generating circuit 10 is coupled to the output terminals of the oscillator 12 and the reset circuit 14. The signal generating circuit 10 generates the switching signal VPWM in response to the clock signal PLS outputted by the oscillator 12. The driving circuit 20 receives the switching signal VPWM for generating a driving signal VG. The driving signal VG is used for controlling switching of the power switch Q1 for regulating the output voltage VO. Because the switching signal VPWM is provided to the driving circuit 20 for generating the driving signal VG, and therefore the switching signal VPWM is used for controlling switching of the power switch Q1. The signal generating circuit 10 adjusts periodically the pulse width of the switching signal VPWM in response to the clear signal CLR outputted by the reset circuit 14. It makes that the output voltage VO of the power supply is regulated stably and the output power is limited.
Referring to FIG. 1, both input terminals of the feedback detection circuit 16 receives respectively the feedback signal VFB and a limit signal VLIMT for generating a pull-high signal SPH. When the power supply operates normally, the feedback signal VFB is lower than the limit signal VLIMT. At this moment, an output terminal of the feedback detection circuit 16 generates the pull-high signal SPH with a low voltage level. The delay circuit 18 does not perform counting, but outputs directly a turn off signal SOFF with a high voltage level to the signal generating circuit 10 when the delay circuit 18 receives the pull-high signal SPH with the low voltage level. The signal generating circuit 10 does not latch the switching signal VPWM when the signal generating circuit 10 receives the turn off signal SOFF with the high voltage level.
When the output terminal of the power supply is open-loop, the voltage level of the feedback signal VFB is pulled to a supply voltage VCC through a pull-up resistor RPH. When the voltage level of the feedback signal VFB is pulled high and higher than the limit signal VLIMT, the output terminal of the feedback detection circuit 16 will generate the pull-high signal SPH with the high voltage level. The delay circuit 18 performs counting in response to the pull-high signal SPH with the high voltage level, and generates the turn off signal SOFF with the low voltage level after the delay circuit 18 counts to a delay time. The signal generating circuit 10 latches the switch signal VPWM in response to the turn off signal SOFF with the low voltage level, which means latching the driving signal VG. Thereby, when the voltage level of the feedback signal VFB is pulled high, the feedback detection circuit 16 and the delay circuit 18 will drive the signal generating circuit 10 to latch the switching signal VPWM for performing the open-loop protection.
Furthermore, when the power supply is short circuited, the voltage level of the feedback signal VFB will also be pulled high to the supply voltage VCC through the pull-up resistor RPH. The feedback detection circuit 16 will then generate the pull-high signal SPH with the high voltage level. The delay circuit 18 will perform counting, and generates the turn off signal SOFF with the low voltage level after the delay circuit 18 counts to the delay time. The signal generating circuit 10 will latch the switching signal VPWM in response to the turn off signal SOFF with the low voltage level for protecting the power supply and the application circuits of the load side. The delay time for short-circuit protection is the same as the delay time for open-loop protection. However, when the power supply is short-circuited, the power supply or the application circuits of the load side can be destroyed in a short time. Therefore, for enhancing safety of the power supply, the signal generating circuit 10 should latch the switching signal VPWM as soon as possible when the power supply is short-circuited. Accordingly, it has become a major subject for modern design of a power supply that the power supply can correctly distinguish between open-loop and short-circuit situations, and can perform short-circuit protection as soon as possible when the power supply is short-circuited.